The present invention relates to methods and apparatus for designing and developing digital signal processing hardware. More specifically, the present invention relates to methods and apparatus for using a system level simulator to generate and simulate hardware designs implementing particular algorithms designed in the system level simulator application.
Simulink® (available from The MathWorks, Inc. of Natick, Mass.) and similar system level simulators allow users to design and simulate Digital Signal Processors. The users design DSP algorithms in these simulators by entering logic blocks and associated connections in a graphical user interface window representing the overall design. System level simulators were traditionally limited to the algorithm development stage of DSP design. As originally implemented, these tools did not handle hardware constraints such as register size, bit width of various words, and the like. Yet logic and arithmetic elements of DSPs are typically implemented as fixed point processing elements employing relatively small word sizes. This is the only cost effective way to create high performance hardware.
Traditional simulators simulate a user's algorithm by executing logic block functions using a full floating-point numeric representation, having a very large dynamic range. Obviously, these simulations will not produce bit and cycle accurate results for the specific hardware design.
Hence, in the traditional scenario, hardware developers were forced to reenter an algorithm design that they had developed in a system level simulator into a hardware design tool such as an HDL based product. Only in this way could the developer obtain an accurate simulation and verification of his or her hardware design. Obviously, the reentry of a previously developed design, which may have been optimized on a full floating point algorithm development tool, was inefficient.
Recently, some products have been introduced to allow some level of hardware development in a system level simulator (specifically Simulink). In these tools, the user can impose some hardware constraints to get a better simulation of the hardware. Examples of such tools include the “System Generator for Simulink” available from Xilinx, Inc. of San Jose, Calif. and the Simulink RTW tools available from The MathWorks, Inc.
Unfortunately, problems remain with these products. First, these products cannot be used to fully design, compile and program the hardware. Second, these products do not allow the designer to introduce floorplan constraints (e.g., pin in and pin out designations, constraints on locations of particular logic or memory elements in the hardware target device, etc.). Still further, these products provide only a very slow simulation of the hardware design itself. This is because they use a bit-by-bit model to generate bit accurate simulations of non-native format words.